Summary
At its SUPERNOVA 2026 event Cerebras unveiled CS-4, a rack-scale AI system built from three new WSE-3 Turbo wafers that delivers 750 PFLOPS of AI compute. Cerebras claims up to 2x the speed of CS-3, up to 30x more tokens per second per user than leading GPU-based solutions, and up to 10x better throughput per watt. Memory bandwidth is 129.6 PB/s, I/O is 7.2 Tb/s, and wafer-to-wafer latency can be as low as two microseconds. The new modular Nexus Platform Architecture adds a pluggable Wafer-Scale Backpack and Direct Wafer Links, supporting models beyond 50 trillion parameters. First shipments are expected this quarter.
Why it matters
This is the first mainstream rack-scale product built by stacking wafers. If the per-user latency and throughput-per-watt claims hold up in independent benchmarks, the economics of latency-sensitive inference (agents, interactive coding, voice) have to be recalculated, and serving dense models beyond 50T parameters becomes easier. All figures are vendor 'up to' claims at announcement — verify independently before planning capacity.
Technical details
| Compute | 750 PFLOPS AI (rack-scale) |
|---|---|
| Wafers | 3x WSE-3 Turbo |
| Claims | up to 2x CS-3 · up to 30x tokens/sec/user vs GPU solutions · up to 10x throughput per watt |
| Memory Bandwidth | 129.6 PB/s |
| Io | 7.2 Tb/s |
| Wafer Latency | as low as 2 microseconds |
| Architecture | modular Nexus Platform Architecture; pluggable Wafer-Scale Backpack; Direct Wafer Links; supports >50T-parameter models |
| Availability | first shipments expected this quarter (Q3 2026) |
| Benchmark Caveat | all figures vendor-claimed at announcement; no independent benchmarks yet |
Updates
2026-08-19 Independent analysis wave post-announcement: SemiAnalysis 'Cerebras's Next Generation CS-4: Fast Just Got Faster' (2026-08-18, coverage-gap recovery — published in the previous window but index-lag prevented capture) concludes CS-4 roughly doubles CS-3 performance mainly via increased power consumption, higher per-wafer clock frequency and rack-scale density rather than a new chip generation ('Double the Performance with Double the Power'); TNW frames it as Cerebras' first multi-wafer system with essentially faster-clocked WSE-3 silicon; TechTimes cites ~4,400 tokens/sec decode (~2x CS-3 token speed, ~6x system-level throughput) with no new silicon (same 5nm wafer, higher clocks); per-wafer figures cited: 44GB on-wafer SRAM, 250 PFLOPS, 43.2 PB/s memory bandwidth. Nexus Platform Architecture details: pluggable Wafer-Scale Backpack, RoCE v2, Direct Wafer Links. Hardware pricing still undisclosed; first-shipments-this-quarter reiterated by HPCwire/IBD/DataCenterDynamics. Also verified: SUPERNOVA 2026 produced no additional product/model announcements beyond CS-4 (investors newsroom + StockTitan CBRS feed checked 2026-08-20). Recommendation stays WATCH pending independent benchmarks and shipment evidence.
2026-08-20 Watch-item re-check (2026-08-20): hardware pricing, independent benchmarks and shipment confirmations remain unavailable (third-party coverage consistently notes all three pending; no MLPerf submissions found). New technical specificity from The Next Platform's analysis: CS-4 machines use an overclocked WSE-3 with the same 900,000 cores, clock speed doubled from 1.4 GHz to 2.8 GHz — mechanically consistent with SemiAnalysis's 'double the performance with double the power' reading (ev-20260818-01 update_2026_08_19). Recommendation stays WATCH pending third-party benchmarks, pricing and first-shipment evidence.
2026-08-30 Hot Chips 2026 deep dive (Cerebras blog, published 2026-08-25; coverage-gap recovery — inside the previous window, first seen 2026-08-30 run): CS-4 power-delivery detail (AC/DC converters ~0.5mm from the wafer, ~100x closer than typical GPU designs, nearly double the power delivery; per-backpack water conditioning with dry quick-disconnects and leak sensors; 277V AC -> 54.5V DC, 5+1/4+1/3+1/4+2 redundancy). Roadmap made public: CS-5 (2027, next-gen WSE) targets up to 10,000 output tok/s/user on open-source models (Gemma 4 31B, gpt-oss-120b) and up to 5,000 tok/s/user on multi-trillion-parameter models (Kimi, GPT-5.6 Sol), 3M tok/s per MW, designed for >50T-param models at interactive speeds; CS-6 combines wafer-scale SRAM/compute with 3D-stacked DRAM for an order-of-magnitude smaller footprint (development began 2024). Also cited: single WSE-3T on-wafer fabric bandwidth 53.5 PB/s vs ~260 TB/s NVLink scale-up for an NVIDIA Rubin NVL72 rack. Watch items unchanged: hardware pricing still undisclosed, no independent benchmarks, no confirmed first shipments (early-access program running); recommendation stays WATCH.
Tags
cerebrascs-4wse-3-turboinferencehardwarewafer-scalesupernova-2026