摘要

Cerebras 在 SUPERNOVA 2026 上发布 CS-4，一套由三片全新 WSE-3 Turbo 晶圆组成的机架级 AI 系统，提供 750 PFLOPS 算力。官方宣称：速度最高为 CS-3 的 2 倍，单用户 token 生成速度最高为主流 GPU 方案的 30 倍，每瓦吞吐最高提升 10 倍。内存带宽 129.6 PB/s，I/O 7.2 Tb/s，晶圆间延迟最低 2 微秒。全新的模块化 Nexus Platform Architecture 采用可插拔的 Wafer-Scale Backpack 和 Direct Wafer Links，可支持超过 50 万亿参数的模型。首批出货预计在本季度。

为什么重要
这是主流厂商第一次把晶圆堆叠做成机架级产品。对做延迟敏感推理（agent、交互式编程、语音）的人来说，如果单用户延迟和每瓦吞吐的宣称在独立 benchmark 中站得住，成本账就要重算了；超过 50 万亿参数的稠密模型 serving 门槛也会被拉低。注意所有数字都是发布时的厂商「最高」口径，做容量规划前必须等独立验证。
技术细节
算力 750 PFLOPS（机架级 AI 算力）
晶圆 3 × WSE-3 Turbo
官方宣称 最高为 CS-3 的 2 倍 · 单用户 token 生成速度最高为 GPU 方案的 30 倍 · 每瓦吞吐最高提升 10 倍
内存带宽 129.6 PB/s
IO 7.2 Tb/s
晶圆间延迟 最低 2 微秒
架构 模块化 Nexus Platform Architecture；可插拔 Wafer-Scale Backpack；Direct Wafer Links；支持 >50T 参数模型
供货 预计本季度（Q3 2026）首批出货
Benchmark 口径 所有数字均为发布时厂商宣称；尚无独立 benchmark
后续更新
2026-08-19 Independent analysis wave post-announcement: SemiAnalysis 'Cerebras's Next Generation CS-4: Fast Just Got Faster' (2026-08-18, coverage-gap recovery — published in the previous window but index-lag prevented capture) concludes CS-4 roughly doubles CS-3 performance mainly via increased power consumption, higher per-wafer clock frequency and rack-scale density rather than a new chip generation ('Double the Performance with Double the Power'); TNW frames it as Cerebras' first multi-wafer system with essentially faster-clocked WSE-3 silicon; TechTimes cites ~4,400 tokens/sec decode (~2x CS-3 token speed, ~6x system-level throughput) with no new silicon (same 5nm wafer, higher clocks); per-wafer figures cited: 44GB on-wafer SRAM, 250 PFLOPS, 43.2 PB/s memory bandwidth. Nexus Platform Architecture details: pluggable Wafer-Scale Backpack, RoCE v2, Direct Wafer Links. Hardware pricing still undisclosed; first-shipments-this-quarter reiterated by HPCwire/IBD/DataCenterDynamics. Also verified: SUPERNOVA 2026 produced no additional product/model announcements beyond CS-4 (investors newsroom + StockTitan CBRS feed checked 2026-08-20). Recommendation stays WATCH pending independent benchmarks and shipment evidence.
2026-08-20 Watch-item re-check (2026-08-20): hardware pricing, independent benchmarks and shipment confirmations remain unavailable (third-party coverage consistently notes all three pending; no MLPerf submissions found). New technical specificity from The Next Platform's analysis: CS-4 machines use an overclocked WSE-3 with the same 900,000 cores, clock speed doubled from 1.4 GHz to 2.8 GHz — mechanically consistent with SemiAnalysis's 'double the performance with double the power' reading (ev-20260818-01 update_2026_08_19). Recommendation stays WATCH pending third-party benchmarks, pricing and first-shipment evidence.
2026-08-30 Hot Chips 2026 deep dive (Cerebras blog, published 2026-08-25; coverage-gap recovery — inside the previous window, first seen 2026-08-30 run): CS-4 power-delivery detail (AC/DC converters ~0.5mm from the wafer, ~100x closer than typical GPU designs, nearly double the power delivery; per-backpack water conditioning with dry quick-disconnects and leak sensors; 277V AC -> 54.5V DC, 5+1/4+1/3+1/4+2 redundancy). Roadmap made public: CS-5 (2027, next-gen WSE) targets up to 10,000 output tok/s/user on open-source models (Gemma 4 31B, gpt-oss-120b) and up to 5,000 tok/s/user on multi-trillion-parameter models (Kimi, GPT-5.6 Sol), 3M tok/s per MW, designed for >50T-param models at interactive speeds; CS-6 combines wafer-scale SRAM/compute with 3D-stacked DRAM for an order-of-magnitude smaller footprint (development began 2024). Also cited: single WSE-3T on-wafer fabric bandwidth 53.5 PB/s vs ~260 TB/s NVLink scale-up for an NVIDIA Rubin NVL72 rack. Watch items unchanged: hardware pricing still undisclosed, no independent benchmarks, no confirmed first shipments (early-access program running); recommendation stays WATCH.
标签
cerebrascs-4wse-3-turboinferencehardwarewafer-scalesupernova-2026