Summary
AMD publishes AMDKernelVault, an open training framework and corpus for HIP and Triton kernel generation on recent CDNA GPUs. The release includes 62,153 execution-verified HIP samples, 39,893 Triton kernels and 2,377 production-grounded ROCm Libraries QA entries. A Qwen3-8B model trained with supervised fine-tuning and execution-aware reinforcement learning leads the compared models on PyTorch-to-HIP, TritonBench-G and ROCmBench correctness under fixed budgets. It does not lead every compilation or speed metric.
Why it matters
For teams building kernel-generation agents, this is the first large execution-verified path that treats AMD hardware as a training target rather than a CUDA afterthought. The released data and Apache-2.0 tooling make a focused ROCm reproduction feasible. Low repository and dataset usage at publication means this is a trial candidate, not an adoption signal.
Technical details
| Corpus | 62,153 execution-verified HIP kernels; 39,893 Triton kernels; 2,377 ROCm Libraries QA entries |
|---|---|
| Pipelines | HIPKernelGen and TritonKernelGen compile, validate and latency-profile generated candidates on AMD hardware |
| Training | Qwen3-8B with supervised fine-tuning plus execution-aware reinforcement learning |
| Results | 34.0% Pass@1 on PyTorch-to-HIP; 33.2% Corr@3 on TritonBench-G; 41.94% Corr@3 on ROCmBench |
| Availability | Apache-2.0 code; public ungated HF dataset; 293 downloads and 2 likes at scan time |
| Limitation | correctness leader under fixed budgets, but not a uniform compilation-rate or speed leader |
Tags
amdrocmhiptritongpu-kernelrlvropen-source