openTPU exposes a complete FPGA accelerator stack with validation across its simulator, physical card and a Hugging Face golden model.
openTPU runs open models on a fully inspectable FPGA accelerator
2026-09-24Frontier watchTRIAL
openTPU publishes an Apache 2.0 accelerator stack spanning SystemVerilog RTL, an instruction set, simulator, compiler, host tools and profiler. The project runs ten open models on a Kintex-7 PCIe FPGA and reports bit-for-bit agreement between the card and simulator. An October 7 update added Hugging Face golden-model validation and fixes from a whole-code assessment.
What this means for you
For inference-infrastructure engineers, this is a compact, inspectable path from model operators to hardware behavior rather than a competitive production accelerator. The unusual FPGA card, vendor toolchain and author-run measurements limit immediate adoption.
FRONTIER WATCH
Public artifacts and validated results are different.
The recorded fact is the public work and its artifacts. Author-reported outcomes do not establish independent reproduction. Next checks include usable code, task conditions and third-party validation.
Evidence & related material
Technical details & scores
| Hardware | Xilinx Kintex-7 xc7k480t PCIe card with two DDR3 channels |
|---|---|
| Stack | SystemVerilog RTL, ISA, bit-exact simulator, kernel language/compiler, host software and profiler |
| Models | Ten open models including Qwen3, Qwen3.5, LFM2.5, Gemma 4, SmolLM3 and Phi-4-mini |
| Reported Validation | Card and ISA simulator produce bit-identical tokens and logits; quantized golden comparison is near its numerical floor |
| Reported Throughput | LFM2.5-230M up to 82.1 wall tok/s; larger models are slower |
| License | Apache 2.0 |
Technical impact 4
Engineering value 4
Adoption signal 2
Maturity 2
Verification cost 3
Risk 3